IEEE Transactions on Parallel and Distributed Systems
Software-Based Rerouting for Fault-Tolerant Pipelined Communication
IEEE Transactions on Parallel and Distributed Systems
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology
IEEE Transactions on Computers
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Fault-tolerant architecture and deflection routing for degradable NoC switches
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SCARAB: a single cycle adaptive routing and bufferless network
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Topology-agnostic fault-tolerant NoC routing method
Proceedings of the Conference on Design, Automation and Test in Europe
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs
Microprocessors & Microsystems
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We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind of reinforcement learning---Q-learning using 2-hop fault information. It is topology-agnostic and insensitive to the shape of the fault region. In order to reduce the routing table size, we also propose a hierarchical Q-learning based deflection routing algorithm (FTDR-H) with area reduction up to 27% for a switch in an 8 x 8 mesh compared to the original FTDR. Experimental results show that in the presence of faults, FTDR and FTDR-H are better than other fault-tolerant deflection routing algorithms and a turn model based fault-tolerant routing algorithm.