An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes
IEEE Transactions on Computers
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Flexible DOR routing for virtualization of multicore chips
SOC'09 Proceedings of the 11th international conference on System-on-chip
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Third International Workshop on Network on Chip Architectures
iFDOR: dynamic rerouting on-chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
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Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.