iFDOR: dynamic rerouting on-chip

Authors:
Frank Olaf Sem-Jacobsen;Samuel Rodrigo;Tor Skeie
Affiliations:
Simula Research Laboratory, Lysaker, Norway;Simula Research Laboratory, Lysaker, Norway;Simula Research Laboratory, Lysaker, Norway and University of Oslo, Norway
Venue:
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Year:
2011

Citing 9
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Abstract

Many-core chip design requires flexible routing solutions for the interconnect to handle faults, provide performance partitions, and react to dynamic changes in processing requirements and power/heat distribution. We have developed a logic based rerouting mechanism suitable for tolerating dynamic powering down of regions within the application partition on the chip. This mechanism is combined with the logic based FDOR routing algorithm to create a powerful routing algorithm with low implementation cost. This allows for higher system utilisation through enabling more efficient power management as well as supporting many irregular mesh topologies through flexible virtualisation. Results show that powering down a single switch results in an 8% throughput reduction in the worst case for the evaluated topology.