Enabling power efficiency through dynamic rerouting on-chip

Authors:
Frank Olaf Sem-Jacobsen;Samuel Rodrigo;Alessandro Strano;Tor Skeie;Davide Bertozzi;Francisco Gilabert
Affiliations:
Simula Research Laboratory;Simula Research Laboratory;University of Ferrara;University of Oslo and Simula Research Laboratory;University of Ferrara;Universidad Politécnica de Valencia
Venue:
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Year:
2013

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Abstract

Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregularities in the commonly used 2-D meshes. In this article, we propose a logic-based routing algorithm, iFDOR, oriented towards dynamic powering down one region within every application partition on the chip through dynamic rerouting, with low implementation costs. Results show that we can successfully shutdown an arbitrary rectangular region within an application partition without significant impact on network performance.