Power gating strategies on GPUs
ACM Transactions on Architecture and Code Optimization (TACO)
Enabling power efficiency through dynamic rerouting on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Energy-aware code motion for GPU shader processors
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Architecture and Code Optimization (TACO)
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As technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low-power GPU (Graphics Processing Unit) focus on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage/Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecturelevel power gating techniques for leakage reduction on GPU. In particular, we focus on the most power-hungry components, shader processors. We observe that, due to different scene complexity, the required shader resources to satisfy the target frame rate actually vary across frames. Therefore, we propose the Predictive Shader Shutdown technique to exploit workload variation across frames for leakage reduction on shader processors. The experimental results show that Predictive Shader Shutdown achieves up to 46% leakage reduction on shader processors with negligible performance degradation.