Flexible DOR routing for virtualization of multicore chips

Authors:
Tor Skeie;Frank Olaf Sem-Jacobsen;Samuel Rodrigo;José Flich;Davide Bertozzi;Simone Medardoni
Affiliations:
Networks and Distributed Systems, Simula Research Laboratory, Lysaker, Norway and Department of Informatics, University of Oslo, Norway;Networks and Distributed Systems, Simula Research Laboratory, Lysaker, Norway;Parallel Architectures Group, Technical University of Valencia, Valencia, Spain;Parallel Architectures Group, Technical University of Valencia, Valencia, Spain;ENDIF, Department of Engineering, University of Ferrara, Ferrara, Italy;ENDIF, Department of Engineering, University of Ferrara, Ferrara, Italy
Venue:
SOC'09 Proceedings of the 11th international conference on System-on-chip
Year:
2009

Citing 9
Cited 8

Processor Allocation in the Mesh Multiprocessors Using the Leapfrog Method

IEEE Transactions on Parallel and Distributed Systems
(R) A Flexible Processor Allocation Strategy for Mesh Connected Parallel Systems

ICPP '96 Proceedings of the Proceedings of the 1996 International Conference on Parallel Processing - Volume 3
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Introduction to the cell multiprocessor

IBM Journal of Research and Development - POWER5 and packaging
An Adaptive Submesh Allocation Strategy for Two-Dimensional Mesh Connected Systems

ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE Micro
An Efficient Implementation of Distributed Routing Algorithms for NoCs

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Isomorphic strategy for processor allocation in k-ary n-cube systems

IEEE Transactions on Computers

Convex-based DOR routing for virtualization of NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
iFDOR: dynamic rerouting on-chip

Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Quest for the ultimate network-on-chip: the NaNoC project

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems

Journal of Parallel and Distributed Computing
Allocating irregular partitions in mesh-based on-chip networks

Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
Topology-agnostic fault-tolerant NoC routing method

Proceedings of the Conference on Design, Automation and Test in Europe
An efficient, low-cost routing framework for convex mesh partitions to support virtualization

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Enabling power efficiency through dynamic rerouting on-chip

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures

Quantified Score

Hi-index	0.00

Visualization

Abstract

The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (Noe). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.