Debug Support for Scalable System-on-Chip
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Flexible DOR routing for virtualization of multicore chips
SOC'09 Proceedings of the 11th international conference on System-on-chip
Microprocessors & Microsystems
An on-chip AHB bus tracer with real-time compression and dynamic multiresolution supports for SoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networks-on-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future systems like virtualization, power, thermal and application management, as well as new challenges in technology scaling like reliability and variability. The introduction of networks-on-chip into the platform enables a component-oriented architectural design which is out of reach of current design methods. This paper presents an overview of the achievements at the end of the second out of three years of planned activities.