A scan cell design for scan-based debugging of an SoC with multiple clock domains
IEEE Transactions on Circuits and Systems II: Express Briefs
Quest for the ultimate network-on-chip: the NaNoC project
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Functional post-silicon diagnosis and debug for networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different ...