Debug Support for Scalable System-on-Chip
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration
Proceedings of the 44th annual Design Automation Conference
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Interactive Debug of SoCs with Multiple Clocks
IEEE Design & Test
An on-chip AHB bus tracer with real-time compression and dynamic multiresolution supports for SoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work proposes a flexible and modular solution for nonintrusive tracing and debugging of software on embedded SoC platforms. It utilizes a separate, dedicated Network-on-Chip (NoC) interconnect with a hierarchical unidirectional ring topology to connect a multitude of monitoring devices. The devices are controlled via a debugger attached to the NoC. They use the network to receive control information and send back observations, which the debugger uses to construct a trace. The system utilizes a very accurate and efficient differential timestamping approach. It allows working with multi-synchronous SoCs, identifying concurrencies and other temporal properties in the SoC and coping with partial power downs and clock gatings. The proposed solution requires a low amount of hardware resources and at the same time provides unmatched capabilities.