A Trace Cache Microarchitecture and Evaluation
IEEE Transactions on Computers - Special issue on cache memory and related problems
Extending Value Reuse to Basic Blocks with Compiler Support
IEEE Transactions on Computers
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
Proceedings of the 45th annual Design Automation Conference
An embedded infrastructure of debug and trace interface for the DSP platform
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
LReplay: a pending period based deterministic replay scheme
Proceedings of the 37th annual international symposium on Computer architecture
Hardware-based data value and address trace filtering techniques
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A reverse-encoding-based on-chip bus tracer for efficient circular-buffer utilization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Deterministic Replay Using Global Clock
ACM Transactions on Architecture and Code Optimization (TACO)
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The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycle-accurate tracing is large and the trace cycle is shallow unless using a proper compression mechanism. In this paper, we propose an embedded multi-resolution AMBA trace analyzer that provides the trade-off between the trace granularity and the trace depth. It consists of two major trace approaches: (1) the signal monitor/tracing which provides the levels of abstraction, and (2) the trace reduction. In the first approach, it allows designers to zoom-in/out to preferred level of abstraction to serve different debugging purposes. In the second approach, the trace analyzer compresses the traced data according to signal characteristics and the cost of on-chip storage is reduced. The trace data will be decompressed on the host for further observation and debugging. The experimental results show that the proposed approach can reach a good compression ratio of 96% and the trace depth is more than two thousand cycles at the higher abstraction level.