Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration
Proceedings of the 44th annual Design Automation Conference
An embedded infrastructure of debug and trace interface for the DSP platform
Proceedings of the 45th annual Design Automation Conference
Generating the trace qualification configuration for MCDS from a high level language
Proceedings of the Conference on Design, Automation and Test in Europe
TraceDo: an on-chip trace system for real-time debug and optimization in multiprocessor soc
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
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The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC). The presented developments support strategy addresses the challenges using both architecture and technology approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The Package Sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.