Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration
Proceedings of the 44th annual Design Automation Conference
A real-time program trace compressor utilizing double move-to-front method
Proceedings of the 46th Annual Design Automation Conference
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
LReplay: a pending period based deterministic replay scheme
Proceedings of the 37th annual international symposium on Computer architecture
Deterministic Replay Using Global Clock
ACM Transactions on Architecture and Code Optimization (TACO)
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The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.