How VSIA Answers the SOC Dilemma
Computer
Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration
Proceedings of the 44th annual Design Automation Conference
First silicon functional validation and debug of multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An embedded infrastructure of debug and trace interface for the DSP platform
Proceedings of the 45th annual Design Automation Conference
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
Proceedings of the 46th Annual Design Automation Conference
Embedded software debugging using virtual filesystem abstractions
Journal of Systems Architecture: the EUROMICRO Journal
Real-time unobtrusive program execution trace compression using branch predictor events
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Hardware-based data value and address trace filtering techniques
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A reverse-encoding-based on-chip bus tracer for efficient circular-buffer utilization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip AHB bus tracer with real-time compression and dynamic multiresolution supports for SoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TraceDo: an on-chip trace system for real-time debug and optimization in multiprocessor soc
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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On-chip program and data tracing is now an essential part of any system level development platform for System-on-Chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each core's debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging Network-on-Chip architectures.