A locally adaptive data compression scheme
Communications of the ACM
MP3: The Definitive Guide
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Novel optical probing technique for flip chip packaged microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Facilitating Rapid First Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Fault Testing and Silicon Debug Using Scan Chains
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series)
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
First silicon functional validation and debug of multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the conference on Design, automation and test in Europe
On Bypassing Blocking Bugs during Post-Silicon Validation
ETS '08 Proceedings of the 2008 13th European Test Symposium
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
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Once a bug is found during post-silicon validation, before committing to a silicon respin of the design it is expected that any other bugs, which have escaped pre-silicon verification, to be also identified. This will minimize the number of respins, which in turn will reduce the implementation costs. However, this is hindered by the presence of blocking bugs in one erroneous module that inhibit the search for bugs in other parts of the chip that process data received from this erroneous module. To address this problem, in this paper we propose a novel embedded debug architecture for bypassing the blocking bugs when dealing with deterministic debug experiments.