ACM Computing Surveys (CSUR)
Hardware-assisted replay of multiprocessor programs
PADD '91 Proceedings of the 1991 ACM/ONR workshop on Parallel and distributed debugging
Reasoning about parallel architectures
Reasoning about parallel architectures
On testing cache-coherent shared memories
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Concepts and Notations for Concurrent Programming
ACM Computing Surveys (CSUR)
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Proceedings of the 30th annual international symposium on Computer architecture
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses
IEEE Design & Test
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Hardware debugging method based on signal transitions and transactions
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
LReplay: a pending period based deterministic replay scheme
Proceedings of the 37th annual international symposium on Computer architecture
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Targeted random test generation for power-aware multicore designs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Deterministic Replay Using Global Clock
ACM Transactions on Architecture and Code Optimization (TACO)
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency, ordering, and atomicity is crucial. X86 microprocessors are prevalent at most levels of computing. Thus, new x86 microprocessors undergo extensive compatibility testing. Being a high volume product, the economic and logistical repercussions of a functional deficiency escaping into the production cycle and beyond are humbling. The first silicon functional validation and debug of multicore microprocessors are constrained by design complexity, compatibility with existing hardware and software, and time-to-market pressures. This paper describes microprocessor debug features and their use in debugging functional failures. An encompassing overview of the microprocessor's first silicon validation is presented. Emphasis is put on validation and debug of multicore microprocessors targeting multinode systems. This paper presents a novel method to validate and debug intra-node and inter-node communication traffic. This paper also develops an analysis to determine optimal on die debug resources. Finally, data from an 8-node system is presented to demonstrate the extent of intrusiveness of a coherent and noncoherent traffic debug feature.