Real-time Emulation Method for ATM Switching Systems in Broadband ISDN
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Rapid System Prototyping for Real-Time Design Validation
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
An SoC design methodology using FPGAs and embedded microprocessors
Proceedings of the 41st annual Design Automation Conference
First silicon functional validation and debug of multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A modeling method by eliminating execution traces for performance evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Coarse-grained simulation method for performance evaluation of a shared memory system
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A model-based method for evaluating embedded system performance by abstraction of execution traces
ECMFA'10 Proceedings of the 6th European conference on Modelling Foundations and Applications
Long-term on-chip verification of systems with logical events scattered in time
Microprocessors & Microsystems
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This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. It can be programmed to generate a trigger for a logic analyzer when it detects certain transitions. The visualizer, which shows the captured data in the matrix, timing-chart, and state-transition diagram formats, helps the engineer effectively find bugs.