The theory of database concurrency control
The theory of database concurrency control
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Linearizability: a correctness condition for concurrent objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improving the accuracy of data race detection
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
Parallel program debugging with on-the-fly anomaly detection
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Proving sequential consistency of high-performance shared memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Sequential consistency versus linearizability (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Detecting violations of sequential consistency
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Detecting data races on weak memory systems
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Checking the correctness of memories
SFCS '91 Proceedings of the 32nd annual symposium on Foundations of computer science
The Stanford Dash Multiprocessor
Computer
Specifying non-blocking shared memories (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
ACM Transactions on Programming Languages and Systems (TOPLAS)
The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
A method for implementing lock-free shared-data structures
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Compile-time support for efficient data race detection in shared-memory parallel programs
PADD '93 Proceedings of the 1993 ACM/ONR workshop on Parallel and distributed debugging
Designing memory consistency models for shared-memory multiprocessors
Designing memory consistency models for shared-memory multiprocessors
ICS '90 Proceedings of the 4th international conference on Supercomputing
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Using “test model-checking” to verify the Runway-PA8000 memory model
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Computation-centric memory models
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
The Complexity of Verifying Memory Coherence and Consistency
IEEE Transactions on Parallel and Distributed Systems
Efficient algorithms for verifying memory consistency
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
First silicon functional validation and debug of multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LReplay: a pending period based deterministic replay scheme
Proceedings of the 37th annual international symposium on Computer architecture
Brief announcement: program regularization in verifying memory consistency
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
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Sequential consistency is the most-widely used correctness condition for multiprocessor memory systems. High-performance shared memory multiprocessors such as the Kendall Square KSR1, the Stanford DASH, and the MIT Alewife employ a variety of techniques to improve memory system performance while providing sequential consistency. Primary among them is the use of caches at each processor, kept coherent by protocols implemented in hardware.We study the problem of testing shared memory multiprocessors to determine if they are indeed providing a sequentially consistent memory. We present a series of results for testing an execution of a shared memory under scenarios that exploit the cache-coherence protocol. In addition to reads and writes to the shared memory, we consider the more powerful read-modify-write, load-reserved, and store-conditional operations available in many cache-coherent multiprocessors.Finally, we consider linearizability, another well-known correctness condition for shared memories. Linearizability imposes additional restrictions on the shared memory, beyond that of sequential consistency; we show that these restrictions are useful in testing such memories.