DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Postsilicon Validation Methodology for Microprocessors
IEEE Design & Test
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Microprocessor Entomology: A Taxonomy of Design Faults in COTS Microprocessors
DCCA '99 Proceedings of the conference on Dependable Computing for Critical Applications
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Verification: what works and what doesn't
Proceedings of the 41st annual Design Automation Conference
SWIFT: Software Implemented Fault Tolerance
Proceedings of the international symposium on Code generation and optimization
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On the cusp of a validation wall
IEEE Design & Test
Processor Verification with hwBugHunt
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
MTV '07 Proceedings of the 2007 Eighth International Workshop on Microprocessor Test and Verification
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Intel's Post Silicon functional validation approach
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Automated Debug of Speed Path Failures Using Functional Tests
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
Proceedings of the 47th Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Releasing efficient beta cores to market early
Proceedings of the 38th annual international symposium on Computer architecture
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliable computing with ultra-reduced instruction set co-processors
Proceedings of the 49th Annual Design Automation Conference
Low cost permanent fault detection using ultra-reduced instruction set co-processors
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
A survey of checker architectures
ACM Computing Surveys (CSUR)
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Microprocessor design validation is a time consuming and costly task that tends to be a bottleneck in the release of new architectures. The validation step that detects the vast majority of design bugs is the one that stresses the silicon prototypes by applying huge numbers of random tests. Despite its bug detection capability, this step is constrained by extreme computing needs for random tests simulation to extract the bug-free memory image for comparison with the actual silicon image. We propose a self-checking method that accelerates silicon validation and significantly increases the number of applied random tests to improve bug detection efficiency and reduce time-to-market. Analysis of four major ISAs (ARM, MIPS, PowerPC, and x86) reveals their inherent diversity: more than three quarters of the instructions can be replaced with equivalent instructions. We exploit this property in post-silicon validation and propose a methodology for the generation of random tests that detect bugs by comparing results of equivalent instructions. We support our bug detection method in hardware with a light-weight mechanism which, in case of a mismatch, replays the random test replacing the offending instruction with its equivalent. Our bug detection method and corresponding hardware significantly accelerate the post-silicon validation process. Evaluation of the method on an x86 microprocessor model demonstrates its efficiency over simulation-based and self-checking alternatives, in terms of bug detection capabilities and validation time speedup.