IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Qualifying Serial Interface Jitter Rapidly and Cost-effectively
Journal of Electronic Testing: Theory and Applications
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Quick detection of difficult bugs for effective post-silicon validation
Proceedings of the 49th Annual Design Automation Conference
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
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Major semiconductor companies experience postsilicon validation turning into an expensive, time-consuming proposition, yet very few college graduates are formally trained in this area. Validation is the activity of ensuring a product satisfies its reference specifications, runs with relevant software and hardware, and meets user expectations. This Perspectives article discusses some of the key challenges to successful validation and shows why a radical transformation is necessary if validation is to be effective in the near future.