DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Shielding against design flaws with field repairable control logic
Proceedings of the 43rd annual Design Automation Conference
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
On the cusp of a validation wall
IEEE Design & Test
Watchdog Processors and Structural Integrity Checking
IEEE Transactions on Computers
Soft-error resilience of the IBM POWER6 processor
IBM Journal of Research and Development
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Online cache state dumping for processor debug
Proceedings of the 46th Annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
Proceedings of the 47th Design Automation Conference
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Proceedings of the 48th Design Automation Conference
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
Lazy suspect-set computation: fault diagnosis for deep electrical bugs
Proceedings of the great lakes symposium on VLSI
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
Specification and synthesis of hardware checkpointing and rollback mechanisms
Proceedings of the 49th Annual Design Automation Conference
Microprocessors & Microsystems
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Space sensitive cache dumping for post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
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The objective of IFRA, Instruction Footprint Recording and Analysis, is to overcome the challenges associated with a very expensive step in post-silicon validation of processors -- bug localization in a system setup. IFRA consists of special design and analysis techniques required to bridge a major gap between system-level and circuit-level debug. Special hardware recorders, called Footprint Recording Structures (FRS's), record semantic information about data and control flows of instructions passing through various design blocks of a processor. This information is recorded concurrently during normal operation of a processor in a post-silicon system validation setup. Upon detection of a problem, the recorded information is scanned out and analyzed for bug localization. Special program analysis techniques, together with the binary of the application executed during post-silicon validation, are used for the analysis. IFRA does not require full system-level reproduction of bugs or system-level simulation. Simulation results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing bugs with very little impact on overall chip area.