Universal classes of hash functions (Extended Abstract)
STOC '77 Proceedings of the ninth annual ACM symposium on Theory of computing
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Software architecture of universal hardware modeler
EURO-DAC '90 Proceedings of the conference on European design automation
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Improved Design Debugging Using Maximum Satisfiability
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Proceedings of the 48th Design Automation Conference
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
Post-silicon fault localisation using maximum satisfiability and backbones
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Lazy suspect-set computation: fault diagnosis for deep electrical bugs
Proceedings of the great lakes symposium on VLSI
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RATS: restoration-aware trace signal selection for post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coverage-based trace signal selection for fault localisation in post-silicon validation
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse. We introduce a new paradigm for using formal analysis, augmented with some on-chip hardware support, to automatically compute error traces that lead to an observed buggy state, thereby greatly simplifying the post-silicon debug problem. Our preliminary simulation experiments demonstrate the potential of our approach: we can "backspace" hundreds of cycles from randomly selected states of some sample designs. Our preliminary architectural studies propose some possible implementations and show that the on-chip overhead can be reasonable. We conclude by surveying future research directions.