Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Diagnosis and correction of multiple logic design errors in digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Beyond verification: leveraging formal for debugging
Proceedings of the 46th Annual Design Automation Conference
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test
IEEE Transactions on Computers
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Fault Localization for Property Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Debugging with dominance: on-the-fly RTL debug solution implications
Proceedings of the International Conference on Computer-Aided Design
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap. Contemporary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task.