Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Algorithms for maximum satisfiability using unsatisfiable cores
Proceedings of the conference on Design, automation and test in Europe
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A dynamic approach to MPE and weighted MAX-SAT
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact multiple-control toffoli network synthesis with SAT techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
sgen1: A generator of small but difficult satisfiability benchmarks
Journal of Experimental Algorithmics (JEA)
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enhancing debugging of multiple missing control errors in reversible logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the Conference on Design, Automation and Test in Europe
Increasing the accuracy of SAT-based debugging
Proceedings of the Conference on Design, Automation and Test in Europe
Sequential logic rectifications with approximate SPFDs
Proceedings of the Conference on Design, Automation and Test in Europe
Combinatorial Optimization Solutions for the Maximum Quartet Consistency Problem
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Integration, the VLSI Journal
Approximate model-based diagnosis using greedy stochastic search
Journal of Artificial Intelligence Research
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Managing complexity in design debugging with sequential abstraction and refinement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Managing SAT inconsistencies with HUMUS
Proceedings of the Sixth International Workshop on Variability Modeling of Software-Intensive Systems
Pipelined microprocessors optimization and debugging
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Debugging with dominance: on-the-fly RTL debug solution implications
Proceedings of the International Conference on Computer-Aided Design
Post-silicon fault localisation using maximum satisfiability and backbones
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Lazy suspect-set computation: fault diagnosis for deep electrical bugs
Proceedings of the great lakes symposium on VLSI
Path directed abstraction and refinement in SAT-based design debugging
Proceedings of the 49th Annual Design Automation Conference
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comparison of strategies for tolerating inconsistencies during decision-making
Proceedings of the 16th International Software Product Line Conference - Volume 1
Compiling finite domain constraints to sat with bee*
Theory and Practice of Logic Programming
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-solution implications using reverse domination in a modern SAT-based debugging environment
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Debugging of inconsistent UML/OCL models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
Partial synthesis through sampling with and without specification
Proceedings of the International Conference on Computer-Aided Design
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Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scale-integration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.