Fault-tolerant computer system design
Fault-tolerant computer system design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diversity Techniques for Concurrent Error Detection
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Verification and Analysis of Self-Checking Properties through ATPG
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
Robustness Check for Multiple Faults Using Formal Techniques
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Automatic Construction of Runtime Monitors for FPGA Based Designs
ISED '11 Proceedings of the 2011 International Symposium on Electronic System Design
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective Robustness Analysis Using Bounded Model Checking Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Circuits which are designed to be dependable are evaluated after gate-level design. For circuits actually implemented in programmable devices, where different fault mechanisms dominate, it is unclear whether such evaluation is relevant. To explore the difference in dependability parameters, we developed a simple method which transforms the evaluation problem into conceptual hardware and then to SAT instances. The method can accommodate any combinational fault model. We evaluated circuits constructed from benchmarks using Modified Duplex Scheme (MDS). The performed evaluation demonstrated that the dependability parameters of the implementations correlate to a significant degree. The number of points vulnerable under the chosen fault models in circuits constructed using the MDS scheme depends much more on the circuit than on implementation type.