TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis

Authors:
Alejandro Czutro;Ilia Polian;Matthew Lewis;Piet Engelke;Sudhakar M. Reddy;Bernd Becker
Affiliations:
-;-;-;-;-;-
Venue:
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Year:
2009

Citing 0
Cited 3

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

Journal of Electronic Testing: Theory and Applications
Incremental solving techniques for SAT-based ATPG

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The influence of implementation type on dependability parameters

Microprocessors & Microsystems

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Abstract

We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.