WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
ACL2 for the verification of fault-tolerance properties: first results
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
RobuCheck: a robustness checker for digital circuits
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems
Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Robustness in the presence of liveness
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
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Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are not available yet. In this paper a formal measure for the robustness of a circuit is introduced. Then, a first algorithm to determine the robustness is presented. This is done by reducing the problem either to sequential equivalence checking or to a sequence of property checking instances. The technique also identifies those parts of the circuit that are not robust from a functional point of view and therefore have to be hardened during layout.