Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Structured Theory Development for a Mechanized Logic
Journal of Automated Reasoning
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A New Approach for Transient Fault Injection Using Symbolic Simulation
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
High-level symbolic simulation for automatic model extraction
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
ACL2 for the verification of fault-tolerance properties: first results
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Complementary Formal Approaches for Dependability Analysis
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Formal Reliability Analysis Using Theorem Proving
IEEE Transactions on Computers
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This work targets the use of formal methods for enhancing dependability analysis of sequential circuits described at the Register Transfer (RT) level. We consider solutions oriented towards theoremproving techniques as an alternative to classical fault-injection techniques, for analyzing the consequences of errors caused by transient faults. A preliminary study was conducted to evaluate the advantages of a highly automated tool like ACL2 in that context. However, this study showed that, in spite of its numerous advantages, the ACL2 logic is not always expressive enough to deal with the properties under consideration here. In this paper, we briefly explain the shortcomings of ACL2 relatively to our problem, and we investigate the application of PVS, thus enabling to improve our simple and multiple faults models and the associated verification methodology1.