Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Evaluation of SET and SEU Effects at Multiple Abstraction Levels
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A New Approach for Transient Fault Injection Using Symbolic Simulation
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
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We target the development of new methodologies for analyzing the robustness of circuits described at the Register Transfer (RT) level, with respect to errors caused by transient faults. Analyzing the potential consequences of errors usually involves fault-injection techniques, using simulation or emulation-based solutions. Our goal is to take advantage of the logical power of theorem proving tools to get alternative solutions that would allow to reason purely symbolically on errors. In this paper we present our preliminary results with the ACL2 theorem prover, in the context of devices that have auto-correction features. First we give a logical definition of the error model as a conjunction of characteristic properties, from which robustness analysis can be performed. Then we improve the methodology to deal with hierarchical systems.