ACL2 for the verification of fault-tolerance properties: first results
Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and its Applications
Towards robustness analysis using PVS
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited bythe shadow of the program image. Another limitation of this approach is the use of extra hardware for fault injection which is not needed during the fault-free running of the design. The aim of this paper is to propose a new approach for transient fault injection based on symbolic simulation and model checking that circumvents the problems experienced due to application dependent fault injection and RTL modification. In this paper we present our approach and analyse the effect of transient faults on the fetch unit of a 32-bit multi-cycle RISC processor. Our approach can be applied generally to any faulty design, not necessarily a processor.