SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Basis for Formal Robustness Checking
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Robustness Check for Multiple Faults Using Formal Techniques
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Circuit Reliability Analysis Using Symbolic Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Continuously shrinking feature sizes lead to an increasing vulnerability of digital circuits. Transient faults may tamper the functionality. Design automation is required to analyze whether faults may induce erroneous output of a circuit. In this paper, the design tool RobuCheck is presented to analyze the influence of transient faults on a circuit's behavior. As a result, the tool identifies components that require protection to obtain fault tolerance. Furthermore, an overall robustness estimation of the circuit is determined.