A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Model checking
A machine program for theorem-proving
Communications of the ACM
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
Propositional Logic: Deduction and Algorithms
Propositional Logic: Deduction and Algorithms
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Search State Equivalence for Redundancy Identification and Test Generation
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SPIRIT: A Highly Robust Combinational Test Generation Algorithm
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Using CSP look-back techniques to solve real-world SAT instances
AAAI'97/IAAI'97 Proceedings of the fourteenth national conference on artificial intelligence and ninth conference on Innovative applications of artificial intelligence
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient reachability checking using sequential SAT
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Unrestricted vs restricted cut in a tableau method for Boolean circuits
Annals of Mathematics and Artificial Intelligence
An efficient test vector generation for checking analog/mixed-signal functional models
Proceedings of the 47th Design Automation Conference
Conflict analysis in mixed integer programming
Discrete Optimization
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
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In this survey, we outline basic SAT- and ATPG- procedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and provide a basic orientation concerning the problem formulations and known approaches in this active field of research.