Design of half-rate clock and data recovery circuits for optical communication systems
Proceedings of the 38th annual Design Automation Conference
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Towards formal verification of analog designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Handbook)
Graph Theory and Its Applications, Second Edition (Discrete Mathematics and Its Applications)
Graph Theory and Its Applications, Second Edition (Discrete Mathematics and Its Applications)
Variable domain transformation for linear PAC analysis of mixed-signal systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Fortifying analog models with equivalence checking and coverage analysis
Proceedings of the 47th Design Automation Conference
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This paper presents an approach to generate test vectors to characterize analog/mixed-signal circuits and its application to check the correspondence between a circuit and its HDL functional model. Interestingly, the abstract behavior of most analog circuits is a linear system, but sometimes only when viewed through a transformation of variables. When linearity holds, validation for the consistency between a circuit and a model can be efficiently performed with a small set of test vectors that grows linearly with the number of analog inputs. The linear abstraction for analog circuits also helps us distinguish different types of analog and digital I/O ports and verify their consistency effectively. We demonstrate the implemented tool by comparing a simple serial link receiver against its functional model.