INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient algorithm for local don't care sets calculation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient Boolean division and substitution
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Integrating symbolic techniques in ATPG-based sequential logic optimization
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Synthesis for multiple input wires replacement of a gate for wiring consideration
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Concurrent D-algorithm on reconfigurable hardware
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Circuit partitioning with coupled logic restructuring techniques
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
Efficient Algorithms for the Inference of Minimum Size DFAs
Machine Learning
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT and ATPG: Boolean engines for formal hardware verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On More Efficient Combinational ATPG Using Functional Learning
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Logic transformation and coding theory-based frameworks for Boolean satisfiability
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Multiple wire reconnections based on implication flow graph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
Rewiring using IRredundancy removal and addition
Proceedings of the Conference on Design, Automation and Test in Europe
Using stålmarck’s algorithm to prove inequalities
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
An overview of parallel SAT solving
Constraints
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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