A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
LOT: Logic Optimization with Testability. New transformations for logic synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VERILAT: verification using logic augmentation and transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a new framework to the solution of Boolean Satisfiability. The first approach is based on certain structural analysis using circuit representation. Here, we convert the given CNF into multilevel circuits based on testability-driven transformation and optimization, and then apply a test technique developed by the authors to verify SAT. This test technique is based on the concepts developed by an earlier-proposed verification tool, VERILAT. Certain algebraic coding theory results are then derived that provide a lower bound on the number of solutions to SAT problems. These proposed frameworks have a real potential for providing new theoretical insights.