Concurrent D-algorithm on reconfigurable hardware

Authors:
Fatih Kocan;Daniel G. Saab
Affiliations:
Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, Ohio;Electrical Engineering and Computer Science Department, Case Western Reserve University, Cleveland, Ohio
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

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Abstract

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an Automatic Test Pattern Generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of speed, and how it compares with software based techniques.