A massively parallel algorithm for fault simulation on the connection machine
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
On efficient concurrent fault simulation for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Dynamic fault diagnosis on reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Concurrent D-algorithm on reconfigurable hardware
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A New Approach to Fault Emulation
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
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In this paper, we propose a method of using an FPGA-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the run-time of fault grading, which is one of the most resource-intensive tasks in the design process. A serial fault emulation algorithm is employed and enhanced by two speed-up techniques. First, a set of independent faults can be emulated in parallel. Second, simultaneous injection of multiple dependent faults is also possible by adding extra supporting circuitry. Because the reconfiguration time spent on mapping the numerous faulty circuits into the FPGA boards could be the bottleneck of the whole process, using extra logic for injecting a large number of faults per configuration can reduce the number of reconfigurations, and thus, significantly improve the efficiency. Some modeling issues that are unique in the fault emulation environment are also addressed. The performance estimation indicates that this approach could be several orders of magnitude faster than the existing software approaches for large designs.