A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Fault emulation: a new approach to fault grading
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Concurrent D-algorithm on reconfigurable hardware
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose an approach to test generation based on reconfigurable devices, emulators, and Field Programmable Gate Arrays (FPGA). This approach is based on automatically designing a circuit which implements the D-algorithm specialized for the circuit under test. This approach exploits fine-grain parallelism in the forward/ backward implications, and conflict checking. In this paper, we show an implementation with a lower hardware overhead than previous approaches making this technique more attractive.