A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A transitive closure based algorithm for test generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Test Propagation Through Modules and Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Practical Scan Test Generation and Application for Embedded FIFOs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Testing nonscan blocks of hardware such as smallembedded memories (register files, etc.) can be done usingexisting scan chains due to the atypically small memorysize. FastScan's Macrotest has been developed to solve thisproblem, and the more interesting problem of concisely andaccurately informing the user about the specific hardwareand command constraints which prevent successful testing.This allows the user to quickly identify the particular problems,and add DFT or change the patterns to match thearchitectural and other restraints of the embedding.