Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Effective march algorithms for testing single-order addressed memories
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Parametric Design of a Built-in Self-Test FIFO Embedded Memory
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
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This paper describes a method for testing non-scanned embedded latch-based FIFOs on an otherwise full-scan chip by using the scan registers thatsurround the FIFO and sharing the test applicationtime with the other ASIC scan tests. The techniqueof excising the FIFOs from the ASIC to allow separate and effective test generation for each is explained, as is the process used to merge the two testsback together for efficient test application. Resultsare presented for three example ASICs which indicate that the method is both efficient and thorough.