A Parametric Design of a Built-in Self-Test FIFO Embedded Memory

Authors:
S. Barbagallo;M. Lobetti Bodoni;D. Medina;G. de Blasio;M. Ferloni;F. Fummi;D. Sciuto
Affiliations:
-;-;-;-;-;-;-
Venue:
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Year:
1996

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Abstract

Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type FIFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-In Self Test architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented.