Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
SWiTEST: a switch level test generation system for CMOS combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast and Accurate CMOS Bridging Fault Simulation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Switch-Level ATPG Using Constraint-Guided Line Justification
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
State persistence: a property for guiding test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault models: stuck-at faults, function conversions, bridging faults, transition faults and faults with additional fault detection conditions. CONTEST is part of a complete test generation system for non-classical faults which consists of a test pattern generator, a fault simulator and a fault list generator. The fault list generator uses a library-based fault modeling strategy which allows the specification of realistic target fault sets. Experimental results show that CONTEST can efficiently handle non-classical faults on the gate level. For a complex target fault set which encompasses for example stuck-at, stuck-open and bridging faults, a test efficiency of 100% has been achieved for each of the ISCAS benchmark circuits containing up to 38,000 nodes.