Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We study a property of circuit states referred to as persistence. The persistence pi(s) of a state s is the number of next-state variables whose values are specified (0 or 1) when a fully-unspecified primary input vector is applied to the circuit in state s. When a next-state variable Yi is specified under a fully-unspecified primary input vector, there are faults in the input cone of Yi that cannot be detected on Yi. We demonstrate through experimental results that when lower-persistence states are used as scan-in states, the resulting tests detect larger numbers of faults. Low-persistence states are thus preferable as scan-in states during test generation. We also discuss the computation of low-persistence states.