Model checking
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Testing of Digital Systems
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Debugging sequential circuits using Boolean satisfiability
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic memory reductions for RTL model verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In today's complex SoC designs, verification and debugging are becoming ever more crucial and increasingly time-consuming tasks. The prevalence of embedded memories adds to the difficulty of the problem by exponentially increasing the statespace of the design. In this work, a novel memory model for design debugging is presented. It models memory succinctly by avoiding an explicit representation for each memory bit. The method uses the simulation of the erroneous design to guide the debugging process. This results in a parameterizable formal encoding that grows linearly with the erroneous trace length, significantly reducing the memory requirements of the debugging problem. In addition, the proposed model is extended to handle an arbitrary initial memory configuration, as well as non-cycle accurate output traces where only a final expected memory state is available for comparison. Experiments on industrial designs show a 96% average reduction in memory usage along with a noticeable performance improvement compared to previous work.