Introduction to algorithms
Model checking and abstraction
POPL '92 Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Algorithms for compacting error traces
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SAT-based counterexample-guided abstraction refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Debugging from high level down to gate level
Proceedings of the 46th Annual Design Automation Conference
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Verification is a major bottleneck in the VLSI design flow with the tasks of error detection, error localization, and error correction consuming up to 70% of the overall design effort. This work proposes a departure from conventional debugging techniques by introducing abstraction and refinement during error localization. Under this new framework, existing debugging techniques can handle large designs with long counter-examples yet remain run time and memory efficient. Experiments on benchmark and industrial designs confirm the effectiveness of the proposed framework and encourage further development of abstraction and refinement methodologies for existing debugging techniques.