Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. B)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Model Checking of Safety Properties
Formal Methods in System Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A comparison of BDDs, BMC, and sequential SAT for model checking
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Experimental analysis of different techniques for bounded model checking
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Compressing BMC Encodings with QBF
Electronic Notes in Theoretical Computer Science (ENTCS)
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Automated deduction for verification
ACM Computing Surveys (CSUR)
CTL model update for system modifications
Journal of Artificial Intelligence Research
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Discrete Event Dynamic Systems
An Optical Wavelength-Based Solution to the 3-SAT Problem
OSC '09 Proceedings of the 2nd International Workshop on Optical SuperComputing
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combining abstraction refinement and SAT-based model checking
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
SAT-based compositional verification using lazy learning
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of safe PLC programs by using Petri nets and formal methods
ICAI'10 Proceedings of the 11th WSEAS international conference on Automation & information
Efficient decision ordering techniques for SAT-based test generation
Proceedings of the Conference on Design, Automation and Test in Europe
Managing verification error traces with bounded model debugging
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IBERAMIA'10 Proceedings of the 12th Ibero-American conference on Advances in artificial intelligence
Managing complexity in design debugging with sequential abstraction and refinement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient self-learning techniques for SAT-based test generation
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An optical solution to the 3-SAT problem using wavelength based selectors
The Journal of Supercomputing
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Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision Diagrams (BDDs) are used to efficiently encode the transition relation of the finite-state model. Recently model checking algorithms based on Boolean satisfiability (SAT) procedures have been developed to complement the traditional BDD-based model checking. These algorithms can be broadly classified into three categories: (1) bounded model checking which is useful for finding failures (2) hybrid algorithms that combine SAT and BDD based methods for unbounded model checking, and (3) purely SAT-based unbounded model checking algorithms. The goal of this paper is to provide a uniform and comprehensive basis for evaluating these algorithms. The paper describes eight bounded and unbounded techniques, and analyzes the performance of these algorithms on a large and diverse set of hardware benchmarks.