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IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
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GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
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Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Can BDDs compete with SAT solvers on bounded model checking?
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic
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VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
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CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
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Logic of Programs, Workshop
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Combination Model Checking: Approach and a Case Study
Proceedings of the 19th IEEE international conference on Automated software engineering
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A work-efficient distributed algorithm for reachability analysis
Formal Methods in System Design
Bounded model checking of infinite state systems
Formal Methods in System Design
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
An improved case-based approach to LTL model checking
RISE'05 Proceedings of the Second international conference on Rapid Integration of Software Engineering Techniques
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
BDD-based Bounded Model Checking for Temporal Properties of 1-Safe Petri Nets
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
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Bounded model checking (BMC) is a procedure that searches for counterexamples to a given property through bounded executions of a non-terminating system. This paper compares the performance of SAT-based, BDD-based and explicit state based BMC on benchmarks drawn from commercial designs. Our experimental framework provides a uniform and comprehensive basis to evaluate each of these approaches. The experimental results in this paper suggest that for designs with deep counterexamples, BDD-based BMC is much faster. For designs with shallow counterexamples, we observe that indeed SAT-based BMC is more effective than BDD-based BMC, but we also observe that explicit state based BMC is comparably effective, a new observation.