Model checking
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
The Impact of Branching Heuristics in Propositional Satisfiability Algorithms
EPIA '99 Proceedings of the 9th Portuguese Conference on Artificial Intelligence: Progress in Artificial Intelligence
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Refining the SAT decision ordering for bounded model checking
Proceedings of the 41st annual Design Automation Conference
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Directed test generation for validation of multicore architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
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Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model checking techniques do not scale well when checking complex designs. In SAT-based BMC, many variable ordering heuristics have been investigated to improve counterexample (test) generation involving only one property. This paper presents efficient decision ordering techniques that can improve the overall test generation time of a cluster of similar properties. Our method exploits the assignments of previously generated tests and incorporates it in the decision ordering heuristic for current test generation. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically reduce the overall test generation time.