Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Contributions of model checking and CoFI methodology to the development of space embedded software
Empirical Software Engineering
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BDD-based model checking and bounded model checking (BMC) are the main techniques currently used in formal verification. In general, there are robustness issues in SAT-based versus BDD-based model checking. The research reported in this paper attempts to analyze the asymptotic run-time behavior of modern BDD-based and SAT based techniques for model checking to determine the circuit characteristics which lead to worst-case behavior in these approaches. We show evidence for a run-time characterization based on sequential correlation and clause density. We demonstrate that it is possible to predict the worst-case behavior of BMC based on these characterizations. This leads to some interesting insights into the behavior of these techniques on a variety of example circuits.