Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Computation of Recurrence Diameters
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Applying SAT Methods in Unbounded Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
SAT-based unbounded symbolic model checking
Proceedings of the 40th annual Design Automation Conference
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Solving Satisfiability in Combinational Circuits
IEEE Design & Test
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Efficient Sequential SAT Solver With Improved Search Strategies
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the 2005 international symposium on Physical design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Sequential equivalence checking based on k-th invariants and circuit SAT solving
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the verification of sequential equivalence
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. We first introduce the notion of th invariants. In contrast to the traditional invariants that hold for all cycles, th invariants are guaranteed to hold only after the th cycle from the initial state. We then present a bounded model checker (BMChecker) and an invariant checker (IChecker), both of which are based on circuit SAT techniques. Jointly, BMChecker and IChecker are used to compute the th invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs that cannot be verified by existing solutions.