Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Constraint synthesis for environment modeling in functional verification
Proceedings of the 40th annual Design Automation Conference
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
The e Language: A Fresh Separation of Concerns
TOOLS '01 Proceedings of the Technology of Object-Oriented Languages and Systems
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Automatic abstraction without counterexamples
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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The modeling of design environments using constraints has gained widespread industrial application, and most verification languages include constructs for specifying constraints. It is therefore critical for verification tools to intelligently leverage constraints to enhance the overall verification process. However, little prior research has addressed the applicability of transformation algorithms to designs with constraints. Even when addressed, prior work lacks optimality and in cases violates constraint semantics. In this paper, we introduce the theory and practice of transformation-based verification in the presence of constraints. We discuss how various existing transformations, such as redundancy removal and retiming, may be optimally applied while preserving constraint semantics, including dead-end states. We additionally introduce novel constraint elimination, introduction, and simplification techniques that preserve property checking. We have implemented all of the techniques proposed in this paper, and have found their synergistic application to be critical to the automated solution of many complex verification problems with constraints.